Abstracts


KEYNOTE - Fundamentals of Computer Redundancy Technique
Dhiraj Pradhan, Bristol, UK
Abstract:
Reliability and availability of computing systems remain major concerns, despite frequent misconceptions that a dramatic increase in component reliability has obviated the need for fault-tolerance. In this talk we will review various threats to system reliability and redundancy techniques for improving reliability. Also we will briefly review models to evaluate reliability.



Combined Effects of Radiation, Electromagnetic Interference and Aging in Modern ICs: Comprehension and Current Solutions
Fabian Vargas, PUCRS, Brazil
Abstract:
This course addresses the background mechanisms inducing aging of very deep submicron (VDSM) integrated circuits (ICs). Issues like ionizing radiation and electromagnetic compatibility (EMC) are presented to underline the effect of aging on the reliability of modern ICs. Laboratory test setup, international standards and electrical models to simulate the combined effects of radiation, EM interference (EMI) and aging are briefly introduced by means of case-studies. Classic design solutions to counteract with aging of VDSM ICs and recent achievements on the development of on-chip aging sensors for leveraging robustness of embedded systems for critical applications are discussed. These sensors are customized for SRAM memories, combinational logic and field-programmable gate arrays (FPGAs).



NBTI Aging in Scaled CMOS Technologies
Victor Champac, INAOE, Mexico
Abstract:
As process technology continues to shrink, process variations and aging effects have an increasing impact on the reliability and performance of manufactured circuits. Aging effects, namely due to Negative Bias Temperature Instability (NBTI) produce performance degradation as time progresses. This degradation rate depends on a) Operational conditions (e.g., VDD, Temperature and time of electrical stress on MOS transistors) and b) Static technological parameters defined in the fabrication process. Moreover, performance of electronic systems for safety-critical applications which operate for many years in harsh environments are more prompt to be impacted by aging. In order to guarantee a safe operation in advanced technologies, aging monitoring should be performed on chip using built-in aging sensors. In this talk, research results on predictive and adaptive aging will be presented. Predictive error detection methodology is  based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI) activated by long lifetime operation.  Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. Also adaptive techniques to improve system performance in the presence of aging are presented.



Challenges in Nano-Scale Integrated Circuits Design: From CMOS to Graphene Devices
Leticia Bolzani Pohls, PUCRS, Brazil
Abstract:
Advances in Very Deep Sub-Micron (VDSM) technology have made possible the integration of millions of transistors into a small area, allowing the increase of the circuits’ density. At each new technology, node delay and supply voltage scale by 30%, performance and transistor density double every two years, and finally the transistor threshold voltage reduces by almost 15%. Although technology scaling has made possible the development of high performance and small size applications for very different uses, it has imposed several challenges related to power consumption, reliability, testing and others. In this scenario, the main goal of this course is to present an introduction about the topic, to introduce the Application-Specific Integrated Circuits (ASICs) design flow and finally, to summarize the main techniques proposed in literature in order to deal with the challenges previously mentioned.



Ionizing Radiation Effects on Integrated Circuits and Test Procedures
Jose Lipovetzky, UBA, Argentina
Abstract:
The exposure of integrated circuits to ionizing radiation causes several effects. In first place, as the Total Ionizing Dose (TID) increases, the circuits suffer an accumulative degradation due to the trapping of electrical charge in the insulators, known as TID effects.Also, the charge deposited by a single heavy ion on a sensitive node in the circuit migh cause soft errors known as Single Event Effects (SEEs). The aim of this presentation is to explain test procedures used for radiation hardness assurance for TID and SEEs. Initially, the physical mechanisms responsible for these effects are explained, to then discuss how the functionality of the irradiated circuits is affected, and finally present and explain the methods used to test an integrated circuit which will be used in a radioactive environment. Also, design techniques used to mitigate TID and SEE effects are presented. Other less frequent effects as displacement damage and destructive single event effects are also presented.



IC Reliability: Failures, Modeling and Characteristics Quantification
Said Hamdioui, TU Delft, Netherlands
Abstract:
No one can deny the fact that we rely heavily on electronic systems in our daily life. It is almost impossible to imagine a day without your smart phone, computers, TV or even your coffee-machine. Without electronics, business/work couldn't continue any more, the quality of education would degenerate, and the life quality probably turn back to the 18th century. Most of us might lose their jobs, because most of current work couldn't hold on in the absence of electronics. Electronic has significantly changed our life!
Designing, verifying, manufacturing and testing such electronics systems are very complex and time consuming processes. This talk starts first with highlighting the fundamental invention that made the electronic system a reality and showing how what a new employee engineer in mid-1958 at Texas Instruments, who did not yet have the right to summer vacation, proved that resistors, transistors and capacitors could exist on the same piece of semiconductor material (i.e. Integrated Circuit IC); an invention that fueled the electronics revolution and even gave Silicon Valley its name. The talk will also highlights the state-of-the art in IC design, test and reliability.
Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced IC and electronics since sixties. Nevertheless, It is well recognized that such scaling has a physical, if not economical, end and it is getting closer to it. The talk will address the scaling and its impact on different aspects of IC and electronics (including design, test and in particular reliability) both for near and long terms.
Different reliability failure mechanisms and the way they are modeled and how they are impacting IC lifetime and degradation will be covered; recent experimental results will be shown for the impact of BTI both on planar CMOS technology as well as on FinFET. Possible ways for the realization of future electronics systems will be discussed.